1. Field of the Invention
Embodiments of the present invention relate to a liquid crystal display device, and more particularly, to an array substrate, a method of manufacturing the same, and a method of repairing a line in the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices are driven based on optical anisotropy and polarization characteristics of a liquid crystal material. Liquid crystal molecules have a long and thin shape, and the liquid crystal molecules are regularly arranged along in an alignment direction. Light passes through the LCD device along the long and thin shape of the liquid crystal molecules. The alignment of the liquid crystal molecules depends on the intensity or the direction of an electric field applied to the liquid crystal molecules. By controlling the intensity or the direction of the electric field, the alignment of the liquid crystal molecules is controlled to display images.
An LCD device of a related art will be described with reference to FIGS. 1 and 2 of the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of an LCD device according to the related art, and FIG. 2 is a plan view of an array substrate for an LCD device according to the related art.
As shown in FIG. 1 and FIG. 2, the LCD device according to the related art includes a lower substrate 22 and an upper substrate 50, with a liquid crystal layer 14 is interposed between the lower substrate 22 and the upper substrate 50. Thin film transistors T, pixel electrodes 46, gate lines 13 and data lines 42 are formed on the lower substrate 22. A black matrix 52, red, green and blue color filters 54a, 54b and 54c and a common electrode 56 are formed on the upper substrate 50. The lower substrate 22 including the thin film transistors T, the pixel electrodes 46, the gate lines 13 and the data lines 42 may be referred to as an array substrate. The upper substrate 50 including the black matrix 52, the color filters 54a, 54b and 54c, and the common electrode 56 may be referred to as a color filter substrate.
The gate lines 13 and the data lines 42 cross each other to define pixel regions P. The thin film transistors T are disposed near respective crossings of the gate and data lines 13 and 42 and are arranged in a matrix.
Each pixel electrode 46 is disposed at each pixel region P and is formed of a transparent conductive material such as indium tin oxide (ITO). The pixel electrodes 46 are connected to the thin film transistors T, respectively. The pixel electrodes 46 are also arranged in a matrix.
Each thin film transistor T includes a gate electrode 30, an active layer 34, and source and drain electrodes 36 and 38. A gate insulating layer 32 is disposed between the gate electrode 30 and the active layer. A passivation layer 40 is disposed between the thin film transistor T and the pixel electrode 46. The gate electrode 30 is connected to the gate line 13 and is supplied with pulse signals from the gate line 13. The source electrode 36 is connected to the data line 42 and is supplied with data signals from the data line 42. The data signals are provided to the pixel electrode 46 through the drain electrode 38 that is spaced apart from the source electrode 36 and that is connected to the pixel electrode 46. The active layer 34 is disposed between the gate electrode 30 and the source and drain electrodes 36 and 38.
The elements of the array substrate may be formed by photolithographic processes. During these processes, the gate line and the data line may be open circuited due to particles generated on a surface of the substrate. In particular, because the data line is formed after other elements are formed, an open circuit is more likely to be formed in the data line than in the gate line